Photolithography is a well-known technique for fabricating integrated circuits by placing a selected pattern on a wafer surface. An image plate having a desired pattern is prepared and placed on a light path created by a light source. The illuminated pattern then passes through an imaging system, typically a lens or a combination of a lens and mirror, for focusing the pattern on a wafer. The wafer is placed on a chuck which securely retains the wafer by creating a vacuum under the wafer. The desired pattern on the image plate is then transferred to a portion of the wafer surface by light passing through the lens and exposing that portion of the wafer surface. In one current system, the entire pattern of the image plate is transferred in one exposure. In another current system, a slit is positioned between the image plate and the wafer. While the wafer and the image plate laterally moves in concert, a strip of the desired pattern passing through the slit exposes the wafer surface until the entire portion of the exposure area is exposed. After the exposure, a stage moves the chuck to a different portion of the wafer surface. The process of exposing the wafer surface is then repeated until all portions of the wafer are exposed. A typical wafer contains one to several hundred chips with each chip having an identical pattern.
As circuit density of integrated circuits has increased over the years, photolithography devices have become increasingly sophisticated. The focus and leveling mechanism has improved a great deal to accommodate the finer resolution present day integrated circuits require. For more precise focus of an image pattern being illuminated on the wafer surface, a modern photolithography device uses a multi-point sensor alignment system to position the wafer under the imaging system and to compensate for the uneven thickness of the wafer. The system first assumes that the focused image of a selected pattern lies flat on a plane and the focal point of every spot on the selected pattern being placed on the wafer surface falls on that plane. Then, the wafer is raised toward or lowered from the imaging system to align the presumed focal plane of the imaging system to the wafer surface. In a current process called field to field leveling, the wafer may also be tilted so that the wafer surface being illuminated is parallel to the presumed flat focal plane of the imaging system.
The assumption of a flat focal plane of the imaging system has been sufficient over the past years. However, as the minimum circuit dimension approaches sub-micron level, that assumption becomes problematic. All lenses have curvature defects and many currently available commercial lenses and focusing systems have a flatness guarantee of about 0.5 micron or, for the best lenses, 0.3 micron. This means that a focal point on the actual focal pattern can deviate from the presumed flat focal plane by as much as 0.5 micron. Further, the 0.5 micron deviation can increase significantly if one or more mirrors are used to reflect light from the light source. In fabricating sub-micron circuits, even a deviation of a fraction of one micron can have a significant effect on accurate transfer of an image pattern leading to poorly defined circuit elements and ultimately lower chip yield.